Moore 序列检测器Moore Sequence Detector (1011)

经典 Moore 型状态机教学示例：检测输入序列 "1011"，输出仅取决于当前状态。

Moorebasicverilog

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Open Source Notice

Source Repository: https://555tools.com

License: MIT

Author: 555Tools Educational

Key Points

- Moore machine: output is function of state only
- Three-segment coding: state reg / next-state / output
- 5 states with overlap detection support
- Synchronous reset, default branch prevents latch

RTL Source

// Copyright (c) 2026 555Tools Educational
// SPDX-License-Identifier: MIT
// Source: https://555tools.com
// Moore FSM Example: 1011 Sequence Detector
// Three-segment coding style (standard for FPGA synthesis)
// 中文：Moore 型状态机教学示例——1011 序列检测器

`timescale 1ns / 1ps

// Moore Machine: Output depends ONLY on current state
// 中文：Moore 机——输出仅取决于当前状态，三段式编码
// Detects sequence "1011" on input x, asserts z=1 when detected
// States: S0(init) -> S1(got 1) -> S2(got 10) -> S3(got 101) -> S4(got 1011)
module moore_seq_detect (
    input  wire clk,        // System clock
    input  wire rst,        // Synchronous reset
    input  wire x,          // Serial input bit
    output reg  z           // Detection output (1 when "1011" found)
);

    // State encoding
    localparam [2:0] S0 = 3'd0,  // Initial / no match
                     S1 = 3'd1,  // Received "1"
                     S2 = 3'd2,  // Received "10"
                     S3 = 3'd3,  // Received "101"
                     S4 = 3'd4;  // Received "1011" (match!)

    reg [2:0] state, next_state;

    // Segment 1: State register (synchronous)
    always @(posedge clk) begin
        if (rst)
            state <= S0;
        else
            state <= next_state;
    end

    // Segment 2: Next-state logic (combinational)
    always @(*) begin
        case (state)
            S0: next_state = x ? S1 : S0;      // Got "1" or stay
            S1: next_state = x ? S1 : S2;      // Got "10" or keep "1"
            S2: next_state = x ? S3 : S0;      // Got "101" or reset
            S3: next_state = x ? S4 : S2;      // Got "1011" or back to "10"
            S4: next_state = x ? S1 : S2;      // After match, check overlap
            default: next_state = S0;
        endcase
    end

    // Segment 3: Moore output logic (depends only on state)
    always @(posedge clk) begin
        if (rst)
            z <= 0;
        else
            z <= (state == S4);  // Output 1 only in S4
    end

endmodule