FPGA Professional Tools
Synthesizable RTL Generator + Annotated Teaching Templates + Visual State Machine Editor
Synthesizable RTL Generator
Three-segment Verilog coding, Moore/Mealy FSM support, binary/one-hot encoding options, generates synthesis-ready RTL code.
Annotated Teaching Template Library
I2C/SPI/UART protocol templates + Moore/Mealy teaching examples, sourced from GitHub open-source projects with annotations and full open-source notices.
Visual State Machine Editor
ReactFlow-based drag-and-drop FSM editor with real-time validation, .fsm.json serialization, and one-click template loading.
Template Library Preview
Synthesizable state machine templates with open-source notices and annotations
I2C Master Controller
Simplified I2C master FSM based on alexforencich/verilog-i2c, supporting full START/STOP/ACK protocol flow.
SPI Master Controller
Simplified SPI master FSM based on janschiefer/verilog_spi, supporting all 4 CPOL/CPHA modes.
UART Transceiver (TX + RX)
UART transceiver based on VLSI-Shubh/UART with 16x oversampling TX/RX and baud rate generator.
Moore Sequence Detector (1011)
Classic Moore FSM teaching example: detects input sequence "1011", output depends only on current state.
Mealy Up/Down Counter
Classic Mealy FSM teaching example: up/down counter control, output depends on state and input.
Professional Value
Expert-backed synthesizable RTL generator + annotated, copy-ready open-source template library = your FPGA development accelerator