FPGA Professional Tools
Synthesizable RTL Generator + Annotated Teaching Templates + Visual State Machine Editor
Synthesizable RTL Generator
Three-segment Verilog coding, Moore/Mealy FSM support, binary/one-hot encoding options, generates synthesis-ready RTL code.
Annotated Teaching Template Library
I2C/SPI/UART protocol templates + Moore/Mealy teaching examples, sourced from GitHub open-source projects with annotations and full open-source notices.
Visual State Machine Editor
ReactFlow-based drag-and-drop FSM editor with real-time validation, .fsm.json serialization, and one-click template loading.
Template Library Preview
Synthesizable state machine templates with open-source notices and annotations
I2C Master Controller
Simplified I2C master FSM based on alexforencich/verilog-i2c, supporting full START/STOP/ACK protocol flow.
SPI Master Controller
555Tools original SPI master FSM supporting all 4 CPOL/CPHA modes with full-duplex shift.
UART Transceiver (TX + RX)
UART transceiver based on VLSI-Shubh/UART with 16x oversampling TX/RX and baud rate generator.
Moore Sequence Detector (1011)
Classic Moore FSM teaching example: detects input sequence "1011", output depends only on current state.
Mealy Up/Down Counter
Classic Mealy FSM teaching example: up/down counter control, output depends on state and input.
2-Flop CDC Synchronizer
Parameterized multi-stage synchronizer for single-bit CDC, default 2 stages configurable to 3/4.
Handshake CDC Synchronizer
Request-acknowledge handshake for safe multi-bit data crossing clock domains.
Asynchronous FIFO (Gray Code Pointer CDC)
Dual-clock asynchronous FIFO with Gray code pointer synchronization and full/empty flags for safe multi-bit data CDC.
Pulse Synchronizer (Toggle + 2-Flop)
Toggle-based pulse synchronizer with 2-flop sync chain, safely transfers single-cycle pulse across clock domains.
Reset Synchronizer (Async Assert / Sync Release)
Async-assert / sync-release reset synchronizer eliminating metastability on reset deassertion; one instance per clock domain.
Button Debouncer
Project F button debouncer with 2-stage sync and counter confirmation, produces ondn/onup one-tick pulses.
Edge Detector
Rising/falling edge detector producing single-cycle pulses for event triggering and synchronization.
Gray Code Converter
Bidirectional Gray code / Binary converter with parameterized width, used in FIFO pointers and encoder interfaces.
PWM Generator
schang412 parametrized PWM generator with prescaler and duty comparison, SystemVerilog enum FSM.
Parallel LFSR
alexforencich parametrizable combinatorial parallel LFSR/CRC with Fibonacci/Galois configuration, purely combinational output.
LFSR CRC Generator
alexforencich LFSR-based parametrizable parallel CRC generator, internally instantiates lfsr module, supports multiple CRC standards.
UART Receiver
alexforencich AXI4-Stream UART receiver with frame/overrun error detection, parametrized data width and prescale.
UART Transmitter
alexforencich AXI4-Stream UART transmitter with backpressure support, parametrized data width and prescale.
I2C Slave
alexforencich simplified I2C slave with 7-bit address matching, byte read/write, and internal memory interface.
Synchronous FIFO
Parameterized synchronous FIFO with configurable width and depth, full/empty flags for same-clock-domain data buffering.
Professional Value
Expert-backed synthesizable RTL generator + annotated, copy-ready open-source template library = your FPGA development accelerator