Tools
Browse all available tools
State Machine Editor
Visual Moore FSM editor + .fsm.json serialization
Timing Diagram Tool
Online digital timing diagram tool based on WaveDrom syntax, SPI/I2C/UART templates, real-time SVG rendering and export
FIFO Depth Calculator
Async/sync FIFO minimum depth estimation with burst/continuous write modes and safety factor
CDC Synchronizer Selector
Recommend correct synchronizer structure for clock-domain crossing, with circuit hints and open-source references
SDC Constraint Generator
Generate standard SDC timing constraints from clock/interface specs with syntax validation
Setup/Hold Checker
Calculate setup/hold slack for a timing path and flag violations
Timing Budget Analyzer
Decompose timing budget across delay segments, compute Fmax & slack
Pipeline Calculator
Calculate throughput and latency from pipeline stages, clock, and initiation interval
AI-Verilog Prompt Workbench
Aggregate open-source mothers' best practices to generate structured Verilog prompts
Verilog Code Template Library
Synthesizable RTL ready to reuse, verified code templates from GitHub open-source projects
Clock Divider Calculator
Integer/non-integer clock division analysis with synthesizable Verilog generation
IEEE 754 Floating-Point Converter
Convert between decimal and IEEE 754 floating-point bit layouts (half/single/double)
Fixed-Point Q Format Converter
Convert between decimal and Qm.n fixed-point with range, resolution, and quantization error
PLL/MMCM Clock Frequency Planner
Calculate MMCM/PLL multiplier and divider parameters (M/D/O) from reference and target frequencies, verify VCO range, generate Clocking Wizard config and SDC constraints
Verilog Coding Style Linter
Paste Verilog code to check coding style compliance with line highlighting, suggestions, and pass rate scoring
CORDIC Calculator
CORDIC iterative algorithm for sin/cos and atan/magnitude with step-by-step convergence visualization and Verilog generation
AXI-Stream Handshake Visualizer
AXI-Stream valid/ready handshake mechanism teaching with 5 classic scenario interactive timing visualization, throughput analysis, and synthesizable handshake RTL
AI-Verilog Coach
Scenario prompt templates → acceptance checklist → AI hallucination/pitfall warnings — a 3-step wizard for better AI-generated Verilog
Video Bandwidth Calculator
Forward/reverse video link bandwidth: resolution × frame rate × bit depth → Gbps, or bandwidth → max FPS
LVDS/SerDes Channel Throughput Calculator
LVDS/SerDes multi-channel net throughput and encoding overhead with reverse channel count and video coverage check
MIPI D-PHY/CSI-2 Throughput Calculator
MIPI D-PHY/CSI-2 payload throughput, max frame rate and lane requirement, supporting RAW8/10/12/16